Clock generation circuit is an important part of the integrated circuit design. As known, external crystals or crystal oscillators used in the circuit can provide an accurate clock source, however, manufacturing cost of the system is increased. Therefore it's necessary to develop an accurate on-chip clock generation circuit. In traditional on-chip high speed clock generation circuits, an LC oscillator is used to obtain a clock with good noise performance, and voltage-controlled capacitors are usually used in the standard CMOS process. Besides, since the LC oscillator is an open-loop design, it usually uses configurable modes to compensate deviation of the clock frequency caused by process variations, and gets a wanted clock frequency by controlling the voltage across the voltage-controlled capacitor to change its capacitance absolute value.
FIG. 1 is a frame diagram of an existing LC oscillator process compensation circuit, as shown is FIG. 1, the existing LC oscillator process compensation circuit includes an LC oscillator, a voltage regulator LDO, and a reference voltage terminal which is arranged for generating a reference voltage vref1. Concretely, two input terminals of the voltage regulator LDO are connected with the reference voltage terminal and an external power source vddl respectively, and an output terminal of the voltage regulator LDO is connected with the LC oscillator, thus the voltage regulator LDO outputs a stable voltage reg1 to the LC oscillator, thereby making it works normally. The LC oscillator includes a gain stage, an inductor L1 and two voltage-controlled capacitors C11 and C12, and the gain stage includes a first Field Effect Transistor M11, a second Field Effect Transistor M12, a third Field Effect Transistor M13 and a fourth Field Effect Transistor M14. Concretely, the first Field Effect Transistor M11 and the second Field Effect Transistor M12 are P-type Field Effect Transistors, and have the same width/length (W/L) ratio; the third Field Effect Transistor M13 and the fourth Field Effect Transistor M14 are N-type Field Effect Transistors, and have the same W/L ratio; the gain stage has two voltage output terminals to output voltage von1 and voltage von2 respectively and correspondingly, and each voltage output terminal is connected with a voltage-controlled capacitor, the inductor L1 is connected between the two voltage output terminals. Specific connections of the above components are showed in FIG. 1, which are not described in detail.
In the above conventional circuit configuration, the voltage difference between two terminals of the voltage-controlled capacitor C11 is von1, and the voltage difference between two terminals of the voltage-controlled capacitor C12 is vop1. When the circuit works normally, a formula related to voltage and current of the Field Effect Transistor is:
      I    =                  1        2            ·      μ      ·              C        ox            ·              W        L            ·                        (                                    V              GS                        -                          V              TH                                )                2              ,wherein μ refers to an electron mobility, more specifically refers to μn for N-type Field Effect Transistors, and refers to μp for P-type Field Effect Transistors; Cox refers to a gate oxide capacitance per unit area;
  W  Lrefers to the width/length ratio of the Field Effect Transistor; VGS refers to a voltage difference between the gate and source of the Field Effect Transistor; VTH refers to a threshold voltage of the Field Effect Transistor, more specifically refers to VTHN for N-type Field Effect Transistors and refers to VTHP for P-type Field Effect Transistors.
In addition, if set a variable
      K    =          μ      ·              C        ox            ·              W        L              ,then:
                    K                  PM          ⁢                                          ⁢          11                    =                        μ          p                ·                  C          ox                ·                              (                          W              L                        )                                PM            ⁢                                                  ⁢            11                                ;                      K                  PM          ⁢                                          ⁢          12                    =                        μ          p                ·                  C          ox                ·                              (                          W              L                        )                                PM            ⁢                                                  ⁢            12                                ;                      K                  NM          ⁢                                          ⁢          13                    =                        μ          n                ·                  C          ox                ·                              (                          W              L                        )                                NM            ⁢                                                  ⁢            13                                ;              K              NM        ⁢                                  ⁢        14              =                  μ        n            ·              C        ox            ·                        (                      W            L                    )                          NM          ⁢                                          ⁢          14                    
According to the size of the Field Effect Transistors mentioned above:
                    (                  W          L                )                    PM        ⁢                                  ⁢        11              =                  (                  W          L                )                    PM        ⁢                                  ⁢        12                                          (                      W            L                    )                          NM          ⁢                                          ⁢          13                    =                        (                      W            L                    )                          NM          ⁢                                          ⁢          14                      ,    and                      μ        p                    μ        n              =                                        (                          W              L                        )                                NM            ⁢                                                  ⁢            13                                                (                          W              L                        )                                PM            ⁢                                                  ⁢            11                              =                                    (                          W              L                        )                                NM            ⁢                                                  ⁢            14                                                (                          W              L                        )                                PM            ⁢                                                  ⁢            12                              
thereby:KPM11=KNM13=KPM12=KNM14 
When calculating DC operating points for the LC oscillator process compensation circuit, the resistance of the inductor L1 is small, the two voltage output terminals are shorted, the first Field Effect Transistor and the second Field Effect Transistor are connected in parallel to form a diode connection, and the third Field Effect Transistor and the fourth Field Effect Transistor are connected in parallel to form a diode connection. During the normal work,
                                                        I                              PM                ⁢                                                                  ⁢                11                                      =                                          1                2                            ·                                                                    K                                          PM                      ⁢                                                                                          ⁢                      11                                                        ⁡                                      (                                                                  V                                                  GS_PM                          ⁢                                                                                                          ⁢                          11                                                                    -                                              V                        THP                                                              )                                                  2                                              ;                ⁢                                  ⁢                              I                          PM              ⁢                                                          ⁢              12                                =                                    1              2                        ·                                                            K                                      PM                    ⁢                                                                                  ⁢                    12                                                  ⁡                                  (                                                            V                                              GS_PM                        ⁢                                                                                                  ⁢                        12                                                              -                                          V                      THP                                                        )                                            2                                                          (        1        )                                                                    I                              NM                ⁢                                                                  ⁢                13                                      =                                          1                2                            ·                                                                    K                                          NM                      ⁢                                                                                          ⁢                      13                                                        ⁡                                      (                                                                  V                                                  GS_NM                          ⁢                                                                                                          ⁢                          13                                                                    -                                              V                        THN                                                              )                                                  2                                              ;                ⁢                                  ⁢                              I                          NM              ⁢                                                          ⁢              14                                =                                    1              2                        ·                                                            K                                      NM                    ⁢                                                                                  ⁢                    14                                                  ⁡                                  (                                                            V                                              GS_NM                        ⁢                                                                                                  ⁢                        14                                                              -                                          V                      THN                                                        )                                            2                                                          (        2        )                                                      V                          GS_PM              ⁢                                                          ⁢              11                                +                      V                          GS_NM              ⁢                                                          ⁢              13                                      =                                            V                              GS_PM                ⁢                                                                  ⁢                12                                      +                          V                              GS_NM                ⁢                                                                  ⁢                14                                              =                      reg            ⁢                                                  ⁢            1                                              (        3        )                                                      I                          NM              ⁢                                                          ⁢              13                                =                      I                          PM              ⁢                                                          ⁢              11                                      ;                              I                          NM              ⁢                                                          ⁢              14                                =                      I                          PM              ⁢                                                          ⁢              12                                                          (        4        )            
Put the formulas (1), (2), (3) into the formula (4), then it can be obtained:
            V              GS_NM        ⁢                                  ⁢        13              =                            reg          ⁢                                          ⁢          1                -                  V          THP                +                  V          THN                    2                  V              GS_NM        ⁢                                  ⁢        14              =                            reg          ⁢                                          ⁢          1                -                  V          THP                +                  V          THN                    2      
The voltage (including the voltage von1 and the voltage vop1) across the voltage-controlled capacitors C11 and C12 are VGS—NM13 and VGS—NM14 respectively, and it can be seen from above formulas that the voltage von1 and the voltage vop1 are related to the threshold voltage of the N-type Field Effect Transistors and the threshold voltage of the P-type Field Effect Transistors. Furthermore, changes of the Field Effect Transistors with the process should be considered in actual manufacturing. And since the process of the N-type Field Effect Transistors and the process of the P-type Field Effect Transistors are not changed simultaneously, so the circuit design should be verified in TT, SS, FF, SF and FS (T represents a standard process corner, S represents a slow process corner, F represents a fast process corner, and N-type Field Effect Transistors are in front with P-type Field Effect Transistors falling behind) process corners for the purpose of covering the entire process changes. From the above results, in the FS and SF process corners, the changes of the voltage von1 and the voltage vop1 are greatest; moreover, in the FS process corner, VTHN=120%·VTHP, and in the SF process corner, VTHN=80%·VTHP, thus in the FS and SF process corners, the voltage von1 and the voltage vop1 respectively as follows:
            V              GS_NM        ⁢                                  ⁢        13              =                  V                  GS_NM          ⁢                                          ⁢          14                    =                                                  reg              ⁢                                                          ⁢              1                        -                          V              THP                        +                          V              THN                                2                =                                            reg              ⁢                                                          ⁢              1                        2                    -                                    20              ⁢                              %                ·                                  V                  THP                                                      2                                          V              GS_NM        ⁢                                  ⁢        13              =                  V                  GS_NM          ⁢                                          ⁢          14                    =                                                  reg              ⁢                                                          ⁢              1                        -                          V              THP                        +                          V              THN                                2                =                                            reg              ⁢                                                          ⁢              1                        2                    +                                    20              ⁢                              %                ·                                  V                  THP                                                      2                              
Since capacitance value of the voltage-controlled capacitors C11 and C12 vary with the voltage von1 and the voltage vop1, so in the FS and SF process corners, the frequency of the LC oscillator will deviate from the design value in the TT process corner, which causes an unstable frequency of the LC oscillator, and makes it difficult to guarantee the working accuracy.
Therefore, it is necessary to provide an improved LC oscillator process compensation circuit to overcome the above drawbacks.